[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Buffering the data bus




I understand that the Etrax100 electrical specs are valid for a load on 
the data bus of 50pF per line.

Our application requires the use of several memory chip - the combined 
effect of which means we are bound to exceed this 50pF limit.

Your datasheet does not specify how to buffer the bidirectional Databus - 
however I believe I have worked out how to do so. I wonder if anyone can 
confirm the following to be correct :

I am dividing the Databus into two buffered sections. One for the EDO 
dynamic RAM and one for the Flash RAM, SRAM and peripherals.

The Buffer on the data bus to the peripherals will normally point outwards 
from the Etrax to the memory and peripherals. This is reversed whenever 
\RD goes low AND a valid chip select signal is present (csp, csr, cse). 

The Buffer on the data bus to the Dram will normally point outwards from 
the Etrax to the DRAM. This is reversed when the relevant CAS goes low 
when both RAS is low and DRAMWE is high. This reversed state persists 
until either DRAMWE goes low or RAS goes high.

My buffers are 8 bit wide and in all the above cases only those bytes 
which are actually being addressed have the buffer "reversed".

Andrew J. Baker
Technical Director
Teledesign PLC
UK