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RE: Parallell port timing


According to our ASIC department the delay is as follows:

<= 50pF load on the pin:

Port G:  1 nop 
Port A:  3 nops
Port B:  1 nop 

> 50pF:

Add 1 nop


-----Original Message-----
From: owner-dev-etrax@xxxxxxx.com]On">mailto:owner-dev-etrax@xxxxxxx.com]On
Behalf Of Anders Blomdell
Sent: Wednesday, March 28, 2001 6:29 PM
To: dev-etrax
Subject: Parallell port timing

What delay can be expected when reading from the general I/O port?

When I connect an output pin on the general port to an input pin, I need a
delay of a few instructions before the result is visible for reading. Is
this maybe a pipelining effect?

What I'm about to do is to enable one of a few external devices, and then
read the result back, like this:

    // How many nop's needed for data to be visible?
    for (i = 0 ; i < 10 ; i++) { asm ("nop"); }
    data = *R_PORT_G_DATA;


Anders Blomdell

 Anders Blomdell
 Department of Automatic Control        Email: anders.blomdell@xxxxxxx.se
 Lund Institute of Technology           Phone: +46 46 222 4625
 Box 118, S-221 00 Lund, Sweden         Fax:   +46 46 138118