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ETRAX100LX CACHE/MMU Interaction...

I am trying to bypass the cache and directly access (no DMA) an external
peripheral device using CSP4 from an ETRAX100LX (v1).

The MMU configuration includes the following:

R_MMU_KSEG = ( (...
                                    ( seg_a,  seg )  |

R_MMU_KBASE_HI = ( (...
                                             ( base_a,  0xa ) |   //
uncached peripheral @0xa0000000

!CSP4, !RD, and !WR were monitored on a digital scope while something
similar to the following loop in a device driver:

while(1) {
   *(0xA0000314) = 1;
   word = *(0xA0000314);

The chip select and write strobe appear to behave as expected, but the read
strobe is only seen once which would indicate that the internal cache is
not bypassed.

I've looked at README.mm as well as Chapter 4 of the ETRAX 100LX Designer's
Reference Manual which states "For detailed information on the MMU
registers, please refer to chapter 19."  which does not appear to be
released yet.

Is there something that I'm missing with respect to ETRAX100LX(v1) internal
cache/MMU interaction?
Hints are welcome.


Tim Stephens
FutureSmart Networks
TEL: 408.997.0586
FAX: 408.997.0588