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Re: bypassing the MMU on the lx chip

I would want to access it from user mode, running a ramdisk on the 128K
SRAM would be acceptable.

I noticed several RAM items in the MTD kernel config such as "support for
ram chips in bus mapping".
I turned all of them on to play and now see 'mtd3: 02000000 00010000 "Raw
memory"' in /proc/mtd.
Does that correspond to /dev/cflash3?   Is it a usable way to access the

Adam Felson
HID Corporation - Engineering
11674 N. Huron Street
Denver, CO 80234-2924
(303) 453-3362

                    Bjorn Wesen                                                              
                    xis.com>              cc:     dev-etrax@xxxxxxx.com                         
                    Sent by:              Subject:     Re: bypassing the MMU on the lx chip  
                    05/11/01 11:50                                                           

On Fri, 11 May 2001, Adam Felson wrote:
> Our company is developing a board with the 100lx chip that has one of the
> memory banks containing 128K SRAM.
> I had always figured that I'd simply put the address into a variable and
> address it indirectly as if that variable had received it's value from
> malloc.
> I think the MMU is going to make that impossible.  Can I bypass memory
> management and access this memory directly?

From a driver or from user-mode ?

Inside the kernel, you just do an ioremap to map any physical memory
section into the kernel-space.

From user-mode it's slightly more complicated - the "right" way to do it
is to write a driver that exports mmap functionality through its
device-node, so user-space mmap's /dev/yourdriver and accesses it, and the
MMU translates that into the SRAM physical adresses using the mapping your
driver code has done.

The bad way of doing it is to do the ioremap but hack the page-table
entries so that they are not kernel-only, and let user-mode use those
"absolute addresses" in some way. That is really bad. :)

User-mode cannot access whole kernel-segments no matter what, so you
cannot bypass the MMU in that sense.