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Re: bypassing the MMU on the lx chip

On Fri, 18 May 2001, Adam Felson wrote:
> I tried using read/write/seeks but I can't seen to do a seek over to the
> sram bank @ 0x0800 0000
> Is there something else I must do to build the kernel to have mtd access @
> 0x0800 0000?

Oh yes.. if you look at arch/cris/README.mm or arch/cris/mm/init.c you'll
notice that the addresses the kernel (and drivers) see are not physical
addresses. The addresses pass through the MMU's 256 MB swapping
translation (for each 256 MB segment, you can choose which physical 256 MB
segment it's mapped to OR if it's going to be page-mapped like user-mode).

The 256 MB segment starting at 0 is referred to in those files as the
flash segment (since flash chips also connect there). The relevant lines
(for the ETRAX 100LX revision 1 chip) are:

                        IO_STATE(R_MMU_KSEG, seg_8, seg  ) |  /* CSE0/1,
flash a
nd I/O */

                        IO_STATE(R_MMU_KSEG, seg_5, seg  ) |  /* cached
flash */

that is, to access 0x0xxxxxxx physical, you need to tell MTD (or any
kernel-space thingy) to look at 0x8xxxxxxx (for uncached access) or
0x5xxxxxxx (for cached access).

If you use 100LX revision 2, the segments are 0xf and 0xe.

Hope this helps,