[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

RE: Configuring sdram and serial ports



Hi,

I have attached the bit allocation for SDRAM_TIMING and
SDRAM_CONFIG.

SDRAM_CONFIG
============
The value for this register depends on the number of row and column 
addresses for the SDRAM. 

It is usually easier to calculate the values if you draw a picture of
the address bits. Example with 9 column addresses and 12 row addresses:

 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
  |  BA |       RA                          |         CA               |  |

Bit 0 : Unused (because the memory is 16 bits)
Bit 1 - 9 : Column address (there are 9 column addresses according to datasheet)
Bit 10 - 21: Row address (12 row addresses according to datasheet)
Bit 22 - 23: Bank addresses (4 banks according to datasheet)

With this picture its quite easy to calculate bank_sel, group_sel, ca and sh.

SDRAM_TIMING
============
The CAS delay is different between SDRAM manufacturers. For most SDRAMs the
following settings can be used for the other bits:

sdram: 1
mrs_data: 0
ref : e13us
ddr: off
clk100: off
ps: off
cmd: 0
pde: 0
rc: 0
rp: 0
rcd: 0

USB and priority
================
USB port 1 can be used simultaneously with ATA. USB port 2 can not be
used simultaneously with ATA. 

The interface priority is:

DMA 0 (Ethernet out)
DMA 1 (Ethernet in)
DMA 8 (USB out)
DMA 9 (USB in)
DMA 2 (Parallel, Serial, SCSI, ATA etc)
DMA 3 (Parallel, Serial, SCSI, ATA etc)
DMA 4 (Parallel, Serial, SCSI, ATA etc)
DMA 5 (Parallel, Serial, SCSI, ATA etc)
DMA 6 (Serial)
DMA 7 (Serial)

Synchronous serial port
=======================
The chapter about synchronous serial ports has not been finished yet. 
The synchronous serial ports are highly configurable to be usable
in a lot of applications. I hope that the example below answers
some of your questions. The register description is available in
the attachment. Can you tell me which device you intend to connect?

mode              master
direction         output
framesync         on
frameyncsize      bit/word
framesynctype     normal
wordsize          8
bitorder          lsb
clk_polarity      neg
frame_polarity    -
status_polarity   normal
clk_driver        normal
frame_driver      normal
status_driver     -

             |                     __|__..._
ssXstatus ___|__________..._______/  |      \____...____________..._______
             |                       |
            _|  _   _   _   _   _   _   _   _   _   _   _   _   _   _   _
ssXclk    _/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/
            _|_ ___ ___     ___ ___ ___     ___         ___ ___     ___
ssXdata   -<_|_X___X___X...X___X___X___X...X___>-...---<___X___X...X___>--
            0|  1   2       7   0   1       7           0   1       7
            lsb             msb lsb         msb         lsb
            _|_                 ___                     ___
ssXframe  _/ | \________...____/   \____...______...___/   \____..._______
(bit)        |
             |
            _|__________   _____________   ____         ________   ____
ssXframe  _/ |          ...             ...    \_...___/        ...    \__
 

Best Regards,
/Mikael

-----Original Message-----
From: owner-dev-etrax@xxxxxxx.com]On">mailto:owner-dev-etrax@xxxxxxx.com]On
Behalf Of Jarkko Tuomi
Sent: Sunday, June 24, 2001 10:59 PM
To: dev-etrax
Subject: Configuring sdram and serial ports



Hello everyone,

How should the R_SDRAM_CONFIG and R_SDRAM_TIMING registers be set for a 16MB
chip connected as in the example "8/16/32 Mbyte (1/2/4Mx16x4)" ?

The designers reference chapter 5 explains the available settings, but the
bit-level information seems to be in the still missing chapter 19.

---

Multiplexed I/O signals - Group D:

It looks like the pins used for USB are intentionally chosen so that they do
not conflict with any of the pins required for ATA channels 0 and 1. This
leads to the assumption that if both interfaces are enabled simultaneously
USB would have a higher priority. Can anyone verify this? The same pattern
repeats in group C for serial port 3.

---

Is there any additional information on the synchronous serial ports? I'd be
particularly interested in how the frame indicator and busy input pins
function, and what the different ioctl options really mean (which clock
polarity "normal" really is, etc..).


Thanks,

Jarkko Tuomi