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Re: Configuring sdram and serial ports

> I have attached the bit allocation for SDRAM_TIMING and

Ok, thanks.

I recompiled the kernel but there still seems to be something wrong,
probably in the HW.
(make xconfig, kernel, files, images)

When I run flashitall, everything seems just fine:

sound:/home/jtuomi/axis/devboard_lx# ./flashitall
* size is 2097176 0x00200018
Using internal boot loader: DBG0 - Debug on ser0.
Starting boot...
We're doing a flash write, this may take up to a few minutes...
Booting device with random id 00002f4f.
Nothing more to read. Read: 2097176/2097176
All written

The trouble is that this takes only 3-4s, but according to the flash
datasheet (TC58FVT160FT-85, same as on devboard_lx) programming should
typically take 15s minimum plus 50s (!) erasing. During this 3-4s, it's
quiet on the /cs and /wr lines. The funny part is that nothing changes even
if I remove the flash chip!

When flashitall returns or when the board is reset, there's activity on
flash /cs and /wr (!) for about 8s. After this /cs for both sdram and flash
remain idle, but the address bus starts to count up, including the sdram
control signals. The frequency varies over a range of approximately 20:1
jumping to a new value at random (abt. 2-20s) intervals. On average it's a
few MHz. Also the step (2 bytes, 4 bytes) varies.

In our application Port A is all GPIO. Some of the pins are configured as
outputs, but they always remain in hi-z. Txd0 is driven high, as is the
sdram clock. However, after flashitall but before reset txd0 is driven
constantly low, and sdram clock is valid.

The power supply is identical to the devboard, and the 3.3V output is clean.
Reset signals are ok. PLL seems to be locked (sdram clock was 50MHz). Total
power consumption is about 1W all the time (cpu, flash, sdram, 10Mbps

I'm kind of running out of ideas, anything?

Jarkko Tuomi