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RE: Serial, DMA problem

It is hard to tell what the problem is. Possible reasons:
1. Another interface/driver that is also using DMA 7 is enabled
2. DMA handling in software is incorrect
3. Hardware problems (are you using developer board?)
Can you send your kernelconfig and your driver?

-----Original Message-----
From: owner-dev-etrax@xxxxxxx.com]On">mailto:owner-dev-etrax@xxxxxxx.com]On Behalf Of Petr Jerabek
Sent: Wednesday, June 27, 2001 2:35 PM
To: dev-etrax
Subject: Serial, DMA problem

Hi all,
We would like to ask you some information.
We need to know some details of DMA transmission of SERIAL0.
DMA doesn't recieve data from SERIAL0 (the receiving is functioning without DMA).
We transmit big block of data (100B-1500B).
DMA FIFO (R_DMA_CH7_STATUS) is still empty, 
R_DMA_CH7_HWSW is also consistent.
SERIAL0 transmitting by DMA is functioning.
Controling of DMA receiving is the same as for DevboardLX - e100boot/cbl -
(net_init, handle_net_read)
- changed for DMA channels 7(in), 6(out) and SERIAL0.
We follow recommended procedure by ET100LX_07_DMA chapter 7.6.1.
Is is needed any special setting or controlling procedure for DMA receiving from SERIAL0?
Thank you again for you answers.
Petr Jerabek 

Our setting:
#define SERIAL_CTRL_W\
     ((IO_STATE(R_SERIAL0_CTRL, tr_baud,       c115k2Hz) /*!!!*/ |\
       IO_STATE(R_SERIAL0_CTRL, rec_baud,      c115k2Hz) /*!!!*/ |\
       IO_STATE(R_SERIAL0_CTRL, dma_err,       ignore)   /*!!!*/ |\
       IO_STATE(R_SERIAL0_CTRL, rec_enable,    enable)   /*!!!*/ |\
       IO_STATE(R_SERIAL0_CTRL, rts_,          active)   |\
       IO_STATE(R_SERIAL0_CTRL, sampling,      middle)   |\
       IO_STATE(R_SERIAL0_CTRL, rec_stick_par, normal)   |\
       IO_STATE(R_SERIAL0_CTRL, rec_par,       even)     |\
       IO_STATE(R_SERIAL0_CTRL, rec_par_en,    disable)  |\
       IO_STATE(R_SERIAL0_CTRL, rec_bitnr,     rec_8bit)) >> 16)
#define SERIAL_CTRL_B \
     ((IO_FIELD(R_SERIAL0_CTRL, txd, 0)                  |\
       IO_STATE(R_SERIAL0_CTRL, tr_enable,     enable)   |\
       IO_STATE(R_SERIAL0_CTRL, auto_cts,      disabled) |\
       IO_STATE(R_SERIAL0_CTRL, stop_bits,     one_bit)  |\
       IO_STATE(R_SERIAL0_CTRL, tr_stick_par,  normal)   |\
       IO_STATE(R_SERIAL0_CTRL, tr_par,        even)     |\
       IO_STATE(R_SERIAL0_CTRL, tr_par_en,     disable)  |\
       IO_STATE(R_SERIAL0_CTRL, tr_bitnr,      tr_8bit)) >> 8)
     (IO_STATE (R_GEN_CONFIG, g24dir,    in)      |\
      IO_STATE (R_GEN_CONFIG, g16_20dir, in)      |\
      IO_STATE (R_GEN_CONFIG, g8_15dir,  in)      |\
      IO_STATE (R_GEN_CONFIG, g0dir,     in)      |\
      IO_STATE (R_GEN_CONFIG, dma9,      usb)     |\
      IO_STATE (R_GEN_CONFIG, dma8,      usb)     |\
      IO_STATE (R_GEN_CONFIG, dma7,      serial0)/*!!!*/ |\
      IO_STATE (R_GEN_CONFIG, dma6,      serial0)/*!!!*/ |\
      IO_STATE (R_GEN_CONFIG, dma5,      par1)  /* Unused, so par1 is ok, =0 */ |\
      IO_STATE (R_GEN_CONFIG, dma4,      par1)  /* Unused, so par1 is ok, =0 */ |\
      IO_STATE (R_GEN_CONFIG, dma3,      scsi0) /* Unused, (must not be 0) */ |\
      IO_STATE (R_GEN_CONFIG, dma2,      scsi0) /* Unused  (must not be 0) */ |\
      IO_STATE (R_GEN_CONFIG, mio_w,     disable) |\
      IO_STATE (R_GEN_CONFIG, ser3,      disable) |\
      IO_STATE (R_GEN_CONFIG, par1,      disable) |\
      IO_STATE (R_GEN_CONFIG, scsi0w,    disable) |\
      IO_STATE (R_GEN_CONFIG, scsi1,     disable) |\
      IO_STATE (R_GEN_CONFIG, mio,       disable) |\
      IO_STATE (R_GEN_CONFIG, ser2,      disable) |\
      IO_STATE (R_GEN_CONFIG, par0,      select)  |\
      IO_STATE (R_GEN_CONFIG, ata,       disable) |\
      IO_STATE (R_GEN_CONFIG, scsi0,     disable))