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Re: Connecting AD-Converter to syncser0
Mikael Starvik wrote:
> The problem may be that the sync serial receiver is started to
> late. The receiver is started the first time read() is called.
> Two possible solutions:
> 1. Open the port in non blocking mode and perform a dummy read
> to start the receiver
> 2. Add SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,rec_enable, enable)
> in your ioctl
I tried both options, but nothing changed. I also disabled DMA but the
DOUT (/rts1) on the dev.board was always high then and did not change
when writing to the port.
> If this doesn't help and will check your software and the connection
> to the AD.
> Consider the sync serial driver experimental. It has not been tested
> in all possible configurations.
> More information about the synchronous serial port can be found
> in the ETRAX 100LX Designer's Reference.
> Hope this helps
> -----Original Message-----
> From: email@example.com]On">mailto:firstname.lastname@example.org]On
> Behalf Of Claudius Moor
> Sent: Friday, July 06, 2001 10:48 AM
> To: dev-etrax
> Subject: Connecting AD-Converter to syncser0
> Hi all,
> I am trying to connect an AD-Converter (MAX1202) over SPI to syncser0.
> For this purpose, I recompiled the kernel with "SyncSer0+DMA enabled". I
> also added an argument (SPI_MBIDIR) to the synchronous serial driver
> (sync_serial.c), which sets the port in MASTER_BIDIR mode when calling
> ioctl(fd, SSP_SPI, SPI_MBIDIR).
> Now, after writing config-data (8 Bit; 0xff for CH7 and external clock
> mode) to syncser0, my AD-converter initializes correctly and sends 12
> bits back to my Dev.Board_lx. The problem is, that I cannot read those
> bits. I am only able to read bits (not the correct values), when setting
> DIN of the AD-converter manually "high" and /CS "low". The converter is
> continuously sampling data and sending on DOUT then.
> Clocking a control byte into DIN starts conversion on the MAX1202. With
> /CS low, each rising edge on SCLK clocks a bit from DIN into the
> internal shift register. After /CS falls, the first logic "1" bit
> defines the control byte's MSB. In external clock mode, the SSTRB output
> pulses high for one clock period before the most significant bit of the
> 12-bit conversion result shifts out of DOUT.
> I connected the AD-converter to the dev.board as follows:
> Dev.Board AD-Converter
> rxd1 (X25/1) <- SSTRB
> /cts1(X25/4) <- DOUT
> txd1 (X25/2) -> CLK
> /rts1(X25/3) -> DIN
> pb4 (X4/7) <- /CS
> Does anyone out there know how to set up syncser0 so that I can read my
> I'm using kernel-2.4.3, Cris compiler 1.11 and Devboard_lx 1.0.0.
> I also attached my application spi.c. It opens syncser0, writes the
> control byte and tries to read the sampled value.
> Many thanks in advance.