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RE: Network connection


Sorry for the late answer. There is no maximum time for
the reset delay.


-----Original Message-----
From: owner-dev-etrax@xxxxxxx.com]On">mailto:owner-dev-etrax@xxxxxxx.com]On
Behalf Of Andrew Baker
Sent: Friday, July 06, 2001 10:31 PM
To: dev-etrax
Subject: RE: Network connection

I notice the chip used to generate the "delayed" reset is a Maxim 833. 
This gives a delay time of 150ms.

Is there any maximum for this reset delay if you want to use the "network 
boot" - or does the code for a network boot in the Axis chip wait until 
the PHY "wakes up" after reset ?

The chip I'd like to use would delay the reset by 250ms and I'm just 
making sure I haven't missed anything critical