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RE: SDRAM



Hi,
 
The information about bit allocations for all register will be published in the Desginer's Reference. I have
attached the information for the SDRAM registers. The SDRAM configs may be a bit tricky to get right.
If you send me a datasheet for your SDRAM I can calculate the values for you.
 
Regards
/Mikael
 
 

-----Original Message-----
From: owner-dev-etrax@xxxxxxx.com]On">mailto:owner-dev-etrax@xxxxxxx.com]On Behalf Of Petr Jerabek
Sent: Thursday, July 12, 2001 1:02 PM
To: dev-etrax
Subject: SDRAM


Hi all,
 
We have a problem with SDRAM configuration. Does enybody have a detailed description of R_SDRAM_CONFIG and R_SDRAM_TIMING registers?
We are using one 4Mx16 100 MHz SDRAM. How should be set these registers?
 
 

R_SDRAM_TIMING
- Write only 
- Address: 0x8
- Initial value: 0x0000FFFF

  Bit:    31    30------16 15-14  13      12     11   10--9   8   7---6
        _______________________________________________________________
       | sdram | mrs_data | ref | ddr | clk100 | ps  | cmd | pde | rc  |
       |_______|__________|_____|_____|________|_____|_____|_____|_____|

  Bit:  5---4 3---2 1---0
        _________________
       | rp  | rcd | cl  |
       |_____|_____|_____|

  Bit:  Name:        Explanation:
  --------------------------------------------------------------------------
     31 sdram        SDRAM enable. This bit must not be set before
                     R_SDRAM_CONFIG is configured properly.
        enable=1
        disable=0
  --------------------------------------------------------------------------
  30-16 mrs_data     Data output on a<15:1> during SDRAM mrs cycle.


  --------------------------------------------------------------------------
  15-14 ref          SDRAM refresh interval. e52us means refresh every 52 us
                     etc.
        e52us=0
        e13us=1
        e6500ns=2
        disable=3
  --------------------------------------------------------------------------
     13 ddr          Double data rate select.

        on=1
        off=0
  --------------------------------------------------------------------------
     12 clk100       SDRAM clock select.

        on=1
        off=0
  --------------------------------------------------------------------------
     11 ps           Power save select.

        on=1
        off=0
  --------------------------------------------------------------------------
   10-9 cmd          Initiate an SDRAM command cycle. The types available are
                     precharge, refresh or mode register set cycle. The ref
        pre=3        and mrs command should always be preceeded by a
        ref=2        precharge command. A command should always be followed
        mrs=1        by a nop command e.g. pre, nop, mrs, nop. This field is
        nop=0        used during initializing of the SDRAM modules.
  --------------------------------------------------------------------------
      8 pde          Power down exit delay. Number of delay cycles will be
                     pde + 1.
        0-1
  --------------------------------------------------------------------------
    7-6 rc           Row cycle time. This is the refresh cycle time and will
                     be rc + 6.
        0-3
  --------------------------------------------------------------------------
    5-4 rp           RAS precharge delay. Number of delay cycles will be rp +
                     1 in 50MHz mode and rp + 2 in 100MHz mode.
        0-3
  --------------------------------------------------------------------------
    3-2 rcd          RAS to CAS delay. Number of delay cycles will be rcd + 1
                     in 50MHz mode and rcd + 2 in 100MHz mode.
        0-3
  --------------------------------------------------------------------------
    1-0 cl           CAS latency. Number of latency cycles will be cl + 1 in
                     50MHz mode and cl + 2 in 100MHz mode. cl = 0 is not
        0-2          allowed in 50MHz mode and cl = 2 is not allowed in
                     100MHz mode i.e. cas latency can be varied from 2 to 3
                     SDRAM clock cycles.
  --------------------------------------------------------------------------

R_SDRAM_CONFIG
- Write only 
- Address: 0xc
- Initial value: Unknown

  Bit:    31     30   29-27 26-24  23     22      21    20-------16 15-13
        _________________________________________________________________
       | wmm1 | wmm0 | sh1 | sh0 |  w  | type1 | type0 | group_sel | ca1 |
       |______|______|_____|_____|_____|_______|_______|___________|_____|

  Bit:  12--------8 7---5 4---------0
        _____________________________
       | bank_sel1 | ca0 | bank_sel0 |
       |___________|_____|___________|

  Bit:  Name:        Explanation:
  --------------------------------------------------------------------------
     31 wmm1         Wide module mode for group 1. In wide module mode, all 8
                     DQM outputs are used in each group. The use of DQM<7:4>
        wmm=1        or DQM<3:0> is selected by the highest address bit in
        norm=0       the selected CAS address range (ca1 field). The ca1
                     field should in this case be set to one bit higher than
                     the highest column address bit to the SDRAM. This mode
                     is used with 64-bit wide SDRAM modules that don't have
                     separate chip selects for the upper and lower half of
                     the data bus.
  --------------------------------------------------------------------------
     30 wmm0         Wide module mode for group 0. See wmm1 for description.

        wmm=1
        norm=0
  --------------------------------------------------------------------------
  29-27 sh1          Row address shift for group 1. 0 == internal address 29-
                     9 is shifted down to pin A21-A1. 7 == internal address
        0-7          29-16 is shifted down to pin A14-A1.
  --------------------------------------------------------------------------
  26-24 sh0          Row address shift for group 0. See sh1 for details.

        0-7
  --------------------------------------------------------------------------
     23 w            DRAM bus width.

        bw16=0
        bw32=1
  --------------------------------------------------------------------------
     22 type1        SDRAM type select for group 1. 2 or 4 banks.

        bank2=0
        bank4=1
  --------------------------------------------------------------------------
     21 type0        SDRAM type select for group 0. 2 or 4 banks.

        bank2=0
        bank4=1
  --------------------------------------------------------------------------
  20-16 group_sel    Selects which address bit that will be used to select
                     between the two groups of SDRAM banks. Always group 0
        grp0=0       (grp0), always group 1 (grp1) or use address bit<value>
        grp1=1       to select between groups. <value> is between 9 and 29.
        bit9=9
        bit10=10
        bit11=11
        bit12=12
        bit13=13
        bit14=14
        bit15=15
        bit16=16
        bit17=17
        bit18=18
        bit19=19
        bit20=20
        bit21=21
        bit22=22
        bit23=23
        bit24=24
        bit25=25
        bit26=26
        bit27=27
        bit28=28
        bit29=29
  --------------------------------------------------------------------------
  15-13 ca1          CAS address range for group 1. This selects how many
                     bits that are used for the column address. 0 == Up to
        0-7          and including address bit 8, 7 == up to and including
                     bit 15.
  --------------------------------------------------------------------------
   12-8 bank_sel1    Selects which address bit that will be used to select
                     between bank 0/1 in group 1. <value> is between 9 and
        bit9=9       29. Bank 2/3 will be controlled by the next higher order
        bit10=10     address bit.
        bit11=11
        bit12=12
        bit13=13
        bit14=14
        bit15=15
        bit16=16
        bit17=17
        bit18=18
        bit19=19
        bit20=20
        bit21=21
        bit22=22
        bit23=23
        bit24=24
        bit25=25
        bit26=26
        bit27=27
        bit28=28
        bit29=29
  --------------------------------------------------------------------------
    7-5 ca0          CAS address range for group 0. See ca1 for details.

        0-7
  --------------------------------------------------------------------------
    4-0 bank_sel0    Selects which address bit that will be used to select
                     between banks 0/1 in group 0. See g1bank_sel for
        bit9=9       details.
        bit10=10
        bit11=11
        bit12=12
        bit13=13
        bit14=14
        bit15=15
        bit16=16
        bit17=17
        bit18=18
        bit19=19
        bit20=20
        bit21=21
        bit22=22
        bit23=23
        bit24=24
        bit25=25
        bit26=26
        bit27=27
        bit28=28
        bit29=29
  --------------------------------------------------------------------------

R_SYNC_SERIAL1_CTRL
- Write only 
- Address: 0x68
- Initial value: Bit 14 and 22 set to 0. Other bits unknown.

  Bit:  31-----28      27      26--24   23         22           21     
        _______________________________________________________________
       | tr_baud | dma_enable | mode | error | rec_enable | f_synctype |
       |_________|____________|______|_______|____________|____________|

  Bit:  20--------19    18        17         16         15         14     
        __________________________________________________________________
       | f_syncsize | f_sync | clk_mode | clk_halt | bitorder | tr_enable |
       |____________|________|__________|__________|__________|___________|

  Bit:  13------11     10          9           8          7     
        ________________________________________________________
       | wordsize | buf_empty | buf_full | flow_ctrl | reserved |
       |__________|___________|__________|___________|__________|

  Bit:        6               5                 4              3      
        ______________________________________________________________
       | clk_polarity | frame_polarity | status_polarity | clk_driver |
       |______________|________________|_________________|____________|

  Bit:        2               1            0     
        _________________________________________
       | frame_driver | status_driver | def_out0 |
       |______________|_______________|__________|

  Bit:  Name:           Explanation:
  --------------------------------------------------------------------------
  31-28 tr_baud         Bit clock if 'baudrate' clock selected in
                        R_SYNC_SERIAL_PRESCALE.
        c150Hz=0
        c300Hz=1
        c600Hz=2
        c1200Hz=3
        c2400Hz=4
        c4800Hz=5
        c9600Hz=6
        c19k2Hz=7
        c28k8Hz=8
        c57k6Hz=9
        c115k2Hz=10
        c230k4Hz=11
        c460k8Hz=12
        c921k6Hz=13
        c3125kHz=14
        reserved=15
  --------------------------------------------------------------------------
     27 dma_enable      Select if interface should transfer data with DMA or
                        by CPU cycles.
        on=1
        off=0
  --------------------------------------------------------------------------
  26-24 mode            'master' == Etrax is generating clock and frame
                        signals. 'slave' == Etrax is lisening to clock and
        master_output=0 frame signals. 'input' == Etrax receives data.
        slave_output=1  'ouput' == Etrax transmits data. 'bidir' == Etrax
        master_input=2  receives and transmits data.  Note: synchrounous
        slave_input=3   serial port pin usage is changed when field 'mode'
        master_bidir=4  is changed, check documentation carefully.
        slave_bidir=5
  --------------------------------------------------------------------------
     23 error           'ignore' == transfer and receiver errors are ignored.
                        status fields underflow and overrun are set but the
        normal=0        transmission is not halted. 'normal' == the
        ignore=1        transmission is stopped when underflow or overrun
                        detected.
  --------------------------------------------------------------------------
     22 rec_enable      Enables/disables incoming data.

        disable=0
        enable=1
  --------------------------------------------------------------------------
     21 f_synctype      'early' == frame sync signal is active 1 bit before
                        first bit in the word. 'normal' == frame sync signal
        normal=0        is active during first bit in the word.
        early=1
  --------------------------------------------------------------------------
  20-19 f_syncsize      'extended' == Frame sync signal is active over the
                        complete word + 1bit. When sending a non interrupted
        bit=0           stream of data frame sync will be continously high.
        word=1          'word' == Frame sync signal is active over the
        extended=2      complete word. 'bit' == Frame sync signal is active
        reserved=3      during first bit in the word.
  --------------------------------------------------------------------------
     18 f_sync          'on' == frame sync is enabled. 'off' == frame sync is
                        ignored, incoming/outgoing data is treated as a
        on=0            bitstream.
        off=1
  --------------------------------------------------------------------------
     17 clk_mode        'normal' == clock is running continously. 'gated' ==
                        clock is gated away when no data transmitted.
        normal=0
        gated=1
  --------------------------------------------------------------------------
     16 clk_halt        'stopped' == frame sync generator is temporary
                        stopped. This is equal to an incoming status signal
        running=0       controlled by the CPU.
        stopped=1
  --------------------------------------------------------------------------
     15 bitorder        Selects if lsb or msb is sent first.

        lsb=0
        msb=1
  --------------------------------------------------------------------------
     14 tr_enable       Enables/disables outgoing data.

        disable=0
        enable=1
  --------------------------------------------------------------------------
  13-11 wordsize        Select word size / data unit size.

        size8bit=0
        size12bit=1
        size16bit=2
        size24bit=3
        size32bit=4
  --------------------------------------------------------------------------
     10 buf_empty       Buffer empty flow control status indicator is active
                        if no more than 0/8 bytes left in the ouptu DMA FIFO.
        lmt_8=0
        lmt_0=1
  --------------------------------------------------------------------------
      9 buf_full        Buffer full flow control status indicator is active
                        if no more than 32/8 bytes of storage available in
        lmt_32=0        the input DMA FIFO.
        lmt_8=1
  --------------------------------------------------------------------------
      8 flow_ctrl       Status input/output signals are read/driven and
                        frame/word start may be delayed if flow_strl enabled.
        disabled=0
        enabled=1
  --------------------------------------------------------------------------
      7 reserved


  --------------------------------------------------------------------------
      6 clk_polarity    Incoming clock sample edge. If negative clock edge is
                        to be used this settings should be 'neg'.
        pos=0
        neg=1
  --------------------------------------------------------------------------
      5 frame_polarity  Polarity of the incoming frame signal. īnormalī ==
                        the frame signal is active high.
        normal=0
        inverted=1
  --------------------------------------------------------------------------
      4 status_polarity Polarity of the incoming status signal. īnormalī ==
                        the status signal is active high.
        normal=0
        inverted=1
  --------------------------------------------------------------------------
      3 clk_driver      Polarity of the outgoing clock signal. 'normal' ==
                        the internal reference clock signal is connected
        normal=0        direct to the clock output. 'inverted' == the
        inverted=1      internal reference clock signal is inverted and
                        connected to the clock output.
  --------------------------------------------------------------------------
      2 frame_driver    Polarity of the outgoing frame signal. 'normal' ==
                        the internal reference frame signal is connected
        normal=0        direct to the status output. 'inverted' == the
        inverted=1      internal reference frame signal is inverted and
                        connected to the frame output.
  --------------------------------------------------------------------------
      1 status_driver   Polarity of the outgoing status signal. 'normal' ==
                        the internal reference status signal is connected
        normal=0        direct to the status output. 'inverted' == the
        inverted=1      internal reference status signal is inverted and
                        connected to the status output.
  --------------------------------------------------------------------------
      0 def_out0        Default value for output 0, if unused.

        high=1
        low=0
  --------------------------------------------------------------------------