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Re: Bcc + nop

> From: Ronny L Nilsson <rln@xxxxxxx.se>
> Date: Wed, 21 Nov 2001 22:59:34 +0100

> I've done some assembler testing with cris and noticed a behaiviour I 
> can't understand. When performing a branch with one of the Bcc 
> commands, a NOP instruction must follow.

Just a note here: it doesn't have to be a NOP instruction.

> Otherwise it doesn't work, 
> howcome?

Branch and return instructions have delay slots, as noted in the
programmers reference manual.  Chapter 2.2.9 "Jump and branch
instructions" refers to Chapter 1.6.1 "Conditional branch" where
there is a detailed description with an example.  Chapter 3
"Bcc" says "The Bcc instruction is a delayed branch instruction,
with one delay slot. Valid instructions for the delay slot are
all instructions except: ...".  I'll forward a request to add a
reference to chapter 1.6.1 there.  (I also noticed the
"Interrupts are disabled until next the instruction." typo:
"... until after the next ...").  Other suggestions to improve
the wording to improve pointing out the delay-slot are most

> Or is it just me?

No, other people also don't read documentation.  Most read the
CPU documentation before they write assembly code, though. :-)
Compiling some C code and looking at the output might also be

brgds, H-P