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RE: EPP problem in LX



Hi Eric,

Sorry that I didn't answer your question yesterday :-)

Information about the parallel port registers and EPP can
be found in the designer's reference:

http://developer.axis.com/doc/hardware/etrax100lx/des_ref/ET100LX_14_Parallel_Ports_010215.pdf

I have also attached the register description for the 
parallel ports. This information will soon be available in
chapter 19 of the designer's reference.

Regards
/Mikael

-----Original Message-----
From: owner-dev-etrax@xxxxxxx.com]On">mailto:owner-dev-etrax@xxxxxxx.com]On
Behalf Of Eric Tang
Sent: Wednesday, December 19, 2001 2:25 AM
To: dev-etrax
Subject: EPP problem in LX


Dear ALL,

	I want to write a device driver to communicate with the device via EPP.
	I can't find any design references on the webpages which describ the
	internal register used by par0/par1. Anyone can tell me how can 
	i write the program for accessing EPP? i also looked at hwtest.c, but
	it seems that it is an old version? and don't have EPP version?
	
	Hope someone can help me.


Regards,
Eric

9. Parallel printer port registers 

--------------------------------------------------------------------------------AXIS                     Register description
COMMUNICATIONS AB                                        Date: Oct 2 2001
                                                   Page:132(422)
--------------------------------------------------------------------------------
9.1 R_PAR0_CTRL_DATA 

- Write only 
- Address: 0x40
- Initial value: Unknown

  Bit:  31------25     24     23------21  20     19      18      17  
        _____________________________________________________________
       | reserved | peri_int | reserved | oe  | seli | autofd | strb |
       |__________|__________|__________|_____|______|________|______|

  Bit:    16   15-------9     8     7----0
        __________________________________
       | init | reserved | ecp_cmd | data |
       |______|__________|_________|______|

  Bit:  Name:        Explanation:
  --------------------------------------------------------------------------
  31-25 reserved

        0
  --------------------------------------------------------------------------
     24 peri_int     Acknowledge peripheral interrupt. This has to be done to
                     enable new interrupts from peripheral units. It should
        ack=1        also be done before the par0_peri interrupt is enabled
        nop=0        the first time to avoid bogus interrupts.
  --------------------------------------------------------------------------
  23-21 reserved

        0
  --------------------------------------------------------------------------
     20 oe           Output enable for data buffer in manual mode.

        enable=1
        disable=0
  --------------------------------------------------------------------------
     19 seli         Controls selectin_ signal in manual mode. `active' ==
                     selectin_ pin low (*).
        active=1
        inactive=0
  --------------------------------------------------------------------------
     18 autofd       Controls autofd_ signal in manual, centronics and IBM
                     fastbyte modes. `active' == autofd_ pin low (*).
        active=1
        inactive=0
  --------------------------------------------------------------------------
     17 strb         Controls strobe_ signal in manual mode. `active' ==
                     strobe_ pin low (*).
        active=1
        inactive=0
  --------------------------------------------------------------------------
     16 init         Controls init_ signal in manual, centronics, IBM
                     fastbyte, nibble and byte modes. `active' == init_ pin
        active=1     low (*).
        inactive=0
  --------------------------------------------------------------------------
   15-9 reserved

        0
  --------------------------------------------------------------------------
      8 ecp_cmd      If the parallel port is in ecp_fwd mode this bit
                     indicates that the byte transmitted is a command. The
        command=1    bit is automatically cleared when the command has been
        data=0       transmitted.
  --------------------------------------------------------------------------
--------------------------------------------------------------------------------AXIS                     Register description
COMMUNICATIONS AB                                        Date: Oct 2 2001
                                                   Page:133(422)
--------------------------------------------------------------------------------  Bit:  Name:        Explanation:
  --------------------------------------------------------------------------
    7-0 data         Data to parallel port data pins in manual mode.


  --------------------------------------------------------------------------

  * == if R_PAR0_CONFIG bit 24-21 are zero. The values of the pins controlled
  by (*) in manual mode are dependent on the value of R_PAR0_CONFIG (bit
  24-21). 
--------------------------------------------------------------------------------AXIS                     Register description
COMMUNICATIONS AB                                        Date: Oct 2 2001
                                                   Page:134(422)
--------------------------------------------------------------------------------
9.2 R_PAR0_CTRL 

- Write only 
- Address: 0x42
- Initial value: Unknown

  Bit:  7--------5 4----0
        _________________
       | reserved | ctrl |
       |__________|______|

  Bit:  Name:        Explanation:
  --------------------------------------------------------------------------
    7-5 reserved

        0
  --------------------------------------------------------------------------
    4-0 ctrl         Bits 20:16 in R_PAR0_CTRL_DATA, i.e. oe, seli, autofd,
                     strb, and init (*).
        0-31
  --------------------------------------------------------------------------

  * == if R_PAR0_CONFIG bit 24-21 are zero. The values of the pins controlled
  by (*) in manual mode are dependent on the value of R_PAR1_CONFIG (bit
  24-21). 
--------------------------------------------------------------------------------AXIS                     Register description
COMMUNICATIONS AB                                        Date: Oct 2 2001
                                                   Page:135(422)
--------------------------------------------------------------------------------
9.3 R_PAR0_STATUS_DATA 

- Read only 
- Address: 0x40
- Initial value: Unknown

  Bit:  31--29   28    27     26     25     24       23        22   
        ____________________________________________________________
       | mode | perr | ack | busy | fault | sel | ext_mode | ecp_16 |
       |______|______|_____|______|_______|_____|__________|________|

  Bit:  21------18    17     16   15-------9     8     7----0
        _____________________________________________________
       | reserved | tr_rdy | dav | reserved | ecp_cmd | data |
       |__________|________|_____|__________|_________|______|

  Bit:  Name:        Explanation:
  --------------------------------------------------------------------------
  31-29 mode         Indicates the current mode. NOTE: The EPP mode-macros
                     are valid if and only if R_PAR0_CONFIG<11> is set. bit
        manual=0     2-0. May be used to detect mode change when the force
        centronics=1 bit in R_PAR0_CONFIG is not set.
        fastbyte=2
        nibble=3
        byte=4
        ecp_fwd=5
        ecp_rev=6
        off=7
        epp_wr1=5
        epp_wr2=6
        epp_wr3=7
        epp_rd=0
  --------------------------------------------------------------------------
     28 perr         The value of the external perror pin (*).

        active=1
        inactive=0
  --------------------------------------------------------------------------
     27 ack          The value of the external ack_ pin (*).

        active=0
        inactive=1
  --------------------------------------------------------------------------
     26 busy         The value of the external busy pin (*).

        active=1
        inactive=0
  --------------------------------------------------------------------------
     25 fault        The value of the external fault_ pin (*).

        active=0
        inactive=1
  --------------------------------------------------------------------------
     24 sel          The value of the external select pin (*).

        active=1
        inactive=0
  --------------------------------------------------------------------------
     23 ext_mode     If ext_mode==0 then everything works as before. i.e. See
                     only the mode field! If ext_mode==1 then if {
        enable=1     ext_mode==1 AND mode==000 ==> epp_read 1000 ext_mode==1
        disable=0    AND mode==101 ==> epp_wr_mode1 1101 ext_mode==1 AND
                     mode==110 ==> epp_wr_mode2 1110 ext_mode==1 AND
                     mode==111 ==> epp_wr_mode3 1111 } else {SHOULD NOT
                     OCCUR!}
  --------------------------------------------------------------------------
--------------------------------------------------------------------------------AXIS                     Register description
COMMUNICATIONS AB                                        Date: Oct 2 2001
                                                   Page:136(422)
--------------------------------------------------------------------------------  Bit:  Name:        Explanation:
  --------------------------------------------------------------------------
     22 ecp_16       If this bit is set the parallel port is acting in ecp16
                     (wide) mode.
        active=1
        inactive=0
  --------------------------------------------------------------------------
  21-18 reserved

        0
  --------------------------------------------------------------------------
     17 tr_rdy       Transmitter ready. Set when it is possible to write a
                     new byte to R_PAR0_DATA when sending.
        ready=1
        busy=0
  --------------------------------------------------------------------------
     16 dav          Data available. Set when there is new data in
                     R_PAR0_DATA when receiving data in non DMA mode.
        data=1
        nodata=0
  --------------------------------------------------------------------------
   15-9 reserved

        0
  --------------------------------------------------------------------------
      8 ecp_cmd      Set when the received byte is an ECP command (in ecp_rev
                     mode only).
        command=1
        data=0
  --------------------------------------------------------------------------
    7-0 data         Latest received data byte.


  --------------------------------------------------------------------------

  * == The value of bit 28-24 in this register may be the inverted value of
  that on the actual pins depending on the setting of R_PAR0_CONFIG (bit
  20-16). 
--------------------------------------------------------------------------------AXIS                     Register description
COMMUNICATIONS AB                                        Date: Oct 2 2001
                                                   Page:137(422)
--------------------------------------------------------------------------------
9.4 R_PAR0_STATUS 

- Read only 
- Address: 0x42
- Initial value: Unknown

  Bit:  15--13   12    11     10      9      8       7         6    
        ____________________________________________________________
       | mode | perr | ack | busy | fault | sel | ext_mode | ecp_16 |
       |______|______|_____|______|_______|_____|__________|________|

  Bit:  5--------2    1       0  
        _________________________
       | reserved | tr_rdy | dav |
       |__________|________|_____|

  Bit:  Name:        Explanation:
  --------------------------------------------------------------------------
  15-13 mode         Indicates the current mode. NOTE: The EPP mode-macros
                     are valid if and only if R_PAR0_CONFIG<11> is set. bit
        manual=0     2-0. May be used to detect mode change when the force
        centronics=1 bit in R_PAR0_CONFIG is not set.
        fastbyte=2
        nibble=3
        byte=4
        ecp_fwd=5
        ecp_rev=6
        off=7
        epp_wr1=5
        epp_wr2=6
        epp_wr3=7
        epp_rd=0
  --------------------------------------------------------------------------
     12 perr         The value of the external perror pin (*).

        active=1
        inactive=0
  --------------------------------------------------------------------------
     11 ack          The value of the external ack_ pin (*).

        active=0
        inactive=1
  --------------------------------------------------------------------------
     10 busy         The value of the external busy pin (*).

        active=1
        inactive=0
  --------------------------------------------------------------------------
      9 fault        The value of the external fault_ pin (*).

        active=0
        inactive=1
  --------------------------------------------------------------------------
      8 sel          The value of the external select pin (*).

        active=1
        inactive=0
  --------------------------------------------------------------------------
      7 ext_mode     If ext_mode==0 then everything works as before. i.e. See
                     only the mode field! If ext_mode==1 then if {
        enable=1     ext_mode==1 AND mode==000 ==> epp_read 1000 ext_mode==1
        disable=0    AND mode==101 ==> epp_wr_mode1 1101 ext_mode==1 AND
                     mode==110 ==> epp_wr_mode2 1110 ext_mode==1 AND
                     mode==111 ==> epp_wr_mode3 1111 } else {SHOULD NOT
                     OCCUR!}
  --------------------------------------------------------------------------
--------------------------------------------------------------------------------AXIS                     Register description
COMMUNICATIONS AB                                        Date: Oct 2 2001
                                                   Page:138(422)
--------------------------------------------------------------------------------  Bit:  Name:        Explanation:
  --------------------------------------------------------------------------
      6 ecp_16       If this bit is set the parallel port is acting in ecp16
                     (wide) mode.
        active=1
        inactive=0
  --------------------------------------------------------------------------
    5-2 reserved

        0
  --------------------------------------------------------------------------
      1 tr_rdy       Transmitter ready. Set when it is possible to write a
                     new byte to R_PAR0_DATA when sending.
        ready=1
        busy=0
  --------------------------------------------------------------------------
      0 dav          Data available. Set when there is new data in
                     R_PAR0_DATA when receiving data in non DMA mode.
        data=1
        nodata=0
  --------------------------------------------------------------------------

  * == The value of bit 28-24 in this register may be the inverted value of
  that on the actual pins depending on the setting of R_PAR0_CONFIG (bit
  20-16). 
--------------------------------------------------------------------------------AXIS                     Register description
COMMUNICATIONS AB                                        Date: Oct 2 2001
                                                   Page:139(422)
--------------------------------------------------------------------------------
9.5 R_PAR_ECP16_DATA 

- Read/Write 
- Address: 0x40
- Initial value: 0

  Bit:  15---0
        ______
       | data |
       |______|

  Bit:  Name:        Explanation:
  --------------------------------------------------------------------------
   15-0 data         Data to parallel port in the wide (ecp-16) mode. Latest
                     written data word (16-b) in the wide mode.

  --------------------------------------------------------------------------
--------------------------------------------------------------------------------AXIS                     Register description
COMMUNICATIONS AB                                        Date: Oct 2 2001
                                                   Page:140(422)
--------------------------------------------------------------------------------
9.6 R_PAR0_CONFIG 

- Write only 
- Address: 0x44
- Initial value: 0

  Bit:  31------26  25     24       23       22      21      20      19  
        _________________________________________________________________
       | reserved | ioe | iseli | iautofd | istrb | iinit | iperr | iack |
       |__________|_____|_______|_________|_______|_______|_______|______|

  Bit:    18       17      16   15------12     11       10     9      8    
        ___________________________________________________________________
       | ibusy | ifault | isel | reserved | ext_mode | wide | dma | rle_in |
       |_______|________|______|__________|__________|______|_____|________|

  Bit:      7        6        5        4            3        2----0
        ___________________________________________________________
       | rle_out | enable | force | ign_ack |        oe_ack | mode |
       |         |        |       |         | epp_addr_data |      |
       |_________|________|_______|_________|_______________|______|

  Bit:  Name:         Explanation:
  --------------------------------------------------------------------------
  31-26 reserved

        0
  --------------------------------------------------------------------------
     25 ioe           Invert the data_oe signal. Set this bit if the output
                      enable signal on the (optional) external driver is
        inv=1         active low.
        noninv=0
  --------------------------------------------------------------------------
     24 iseli         Invert the selectin_ signal. If the seli bit in the
                      R_PAR1_CTRL register is set to one the selectin_ pin
        inv=1         will be set to one if this bit is set (manual mode).
        noninv=0
  --------------------------------------------------------------------------
     23 iautofd       As iseli, but for the autofd_ signal.

        inv=1
        noninv=0
  --------------------------------------------------------------------------
     22 istrb         As iseli, but for the strobe_ signal.

        inv=1
        noninv=0
  --------------------------------------------------------------------------
     21 iinit         As iseli, but for the init_ signal.

        inv=1
        noninv=0
  --------------------------------------------------------------------------
     20 iperr         Invert the perror signal. If the perror pin is one and
                      this bit is set, the perr bit in R_PAR0_STATUS will be
        inv=1         zero.
        noninv=0
  --------------------------------------------------------------------------
     19 iack          As iperr, but for the ack_ signal.

        inv=1
        noninv=0
  --------------------------------------------------------------------------
--------------------------------------------------------------------------------AXIS                     Register description
COMMUNICATIONS AB                                        Date: Oct 2 2001
                                                   Page:141(422)
--------------------------------------------------------------------------------  Bit:  Name:         Explanation:
  --------------------------------------------------------------------------
     18 ibusy         As iperr, but for the busy_ signal.

        inv=1
        noninv=0
  --------------------------------------------------------------------------
     17 ifault        As iperr, but for the fault_ signal.

        inv=1
        noninv=0
  --------------------------------------------------------------------------
     16 isel          As iperr, but for the select signal.

        inv=1
        noninv=0
  --------------------------------------------------------------------------
  15-12 reserved

        0
  --------------------------------------------------------------------------
     11 ext_mode      Enables the EPP rd/wr modes. This bit will be placed as
                      the 4th bit of the mode field "R_PAR0_CONFIG<2:0>". If
        enable=1      ext_mode==0 then everything works as before. If
        disable=0     ext_mode==1 then if If {  ext_mode==1 AND mode==000 ==>
                      epp_read 1000  ext_mode==1 AND mode==101 ==>
                      epp_wr_mode1 1101  ext_mode==1 AND mode==110 ==>
                      epp_wr_mode2 1110  ext_mode==1 AND mode==111 ==>
                      epp_wr_mode3 1111 } else {SHOULD NOT OCCUR!}
  --------------------------------------------------------------------------
     10 wide          Enables 16-bits mode in ECP. Note! Both bit-31 (par_w
                      field) in the R_GEN_CONFIG and bit-2 (par0 field) in
        enable=1      the R_GEN_CONFIG must also been set, in order to
        disable=0     activate the wide-mode in the parallel port.
  --------------------------------------------------------------------------
      9 dma           Enable dma mode. Data will be sent received using dma.

        enable=1
        disable=0
  --------------------------------------------------------------------------
      8 rle_in        Enable ECP RLE expansion on incoming data.

        enable=1
        disable=0
  --------------------------------------------------------------------------
      7 rle_out       Enable ECP RLE compression on outgoing data.

        enable=1
        disable=0
  --------------------------------------------------------------------------
      6 enable        Enable/reset parallel port.

        on=1
        reset=0
  --------------------------------------------------------------------------
      5 force         Force mode change to happen immediately, instead of at
                      next idle state. I.e. if mode is changed without this
        on=1          bit set, the change of mode will happen when the port
        off=0         has finished the current handshake. To detect when the
                      mode has changed, R_PAR0_STATUS must be read.
  --------------------------------------------------------------------------
--------------------------------------------------------------------------------AXIS                     Register description
COMMUNICATIONS AB                                        Date: Oct 2 2001
                                                   Page:142(422)
--------------------------------------------------------------------------------  Bit:  Name:         Explanation:
  --------------------------------------------------------------------------
      4 ign_ack       Ignore the ack_ signal in centronics mode. oe_ack may
                      not be set to wait_oe for this to work. No effect in
        ignore=1      the other modes.
        wait=0
  --------------------------------------------------------------------------
      3 oe_ack        Centronics mode: Output data until ack_ goes low.
        epp_addr_data ign_ack may not be set for this to work. EPP mode:
                      epp_addr_data==1 => epp_addr, epp_addr_data==0 =>
        wait_oe=1     epp_data
        dont_wait=0
        epp_addr=1
        epp_data=0
  --------------------------------------------------------------------------
    2-0 mode          Select parallel port mode. In off mode the parallel
                      port output signals are set as follows: selectin_ = 0
        manual=0      (IEEE-1284 inactive), autofd_ = 1 (inactive), strobe_ =
        centronics=1  1 (inactive),init_ = 1 (inactive). This mode can be
        fastbyte=2    used to initiate IEEE-1284 termination phase.
        nibble=3      Important: In order to operate in EPP mode bit 11
        byte=4        (ext_mode) must be set.
        ecp_fwd=5
        ecp_rev=6
        off=7
        epp_wr1=5
        epp_wr2=6
        epp_wr3=7
        epp_rd=0
  --------------------------------------------------------------------------
--------------------------------------------------------------------------------AXIS                     Register description
COMMUNICATIONS AB                                        Date: Oct 2 2001
                                                   Page:143(422)
--------------------------------------------------------------------------------
9.7 R_PAR0_DELAY 

- Write only 
- Address: 0x48
- Initial value: Unknown

  Bit:  31------24 23-------21 20--16 15-------13 12-----8 7----------5
        _______________________________________________________________
       | reserved | fine_hold | hold | fine_strb | strobe | fine_setup |
       |__________|___________|______|___________|________|____________|

  Bit:  4-----0
        _______
       | setup |
       |_______|

  Bit:  Name:        Explanation:
  --------------------------------------------------------------------------
  31-24 reserved

        0
  --------------------------------------------------------------------------
  23-21 fine_hold    Fine tunes the hold time; the 3 ls-bits in the counter.


  --------------------------------------------------------------------------
  20-16 hold         Hold time (time after strobe goes inactive until data is
                     no longer valid) in centronics mode; the 5 ms-bits in
                     the counter. Hold_time = (field_value * 160 +
                     fine_field_value * 20 + 20) ns, i.e. 20ns-5.1us.
  --------------------------------------------------------------------------
  15-13 fine_strb    Fines tunes the strobe time; the 3 ls-bits in the
                     counter.

  --------------------------------------------------------------------------
   12-8 strobe       Strobe time (time the strobe signal is active) in
                     centronics mode; the 5 ms-bits in the counter.
                     Strobe_time = (field_value * 160 + fine_field_value * 20
                     + 20) ns, i.e. 20ns-5.1us.
  --------------------------------------------------------------------------
    7-5 fine_setup   Fine tunes the setup time; the 3 ls-bits in the counter.


  --------------------------------------------------------------------------
    4-0 setup        Setup time (time from data out to strobe) in ECP
                     forward, centronics and IBM fastbyte modes; the 5 ms-
                     bits in the counter. Set_time = (field_value * 160 +
                     fine_field_value * 20 + 10) ns, i.e. 10ns-5us.
  --------------------------------------------------------------------------

  Example. If setup is set to 00010 (0x2) and the fine_setup is set to 001
  (0x1), the setup time will be then (2 * 160 + 1 * 20 + 10) = 350ns.