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How does clk gated work?


We are using synchronus port 1 in master output mode.

Our problem is that the clock and frame sync is sent as soon as we turn
the serial port on. We only want them when actual data is sent.

We looked in the datasheets and found a clk gated option which
(as we understood) would do what we wanted.

But on our oscilloscope it seems like it's sending clk and frame sync
as soon as we enable clk running and tr enable.

Are we doing anything wrong?

Anders Hasselqvist/Björn Yttergren