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RE: How does clk gated work?


Are you running in DMA or manual mode? Can you send me the values
you write to R_SYNC_SERIAL1_CTRL? I know that I have tested
gated clock once and that it worked as expected. 

Note that you have to disable serial port 1 in kernelconfig
to run synchronous serial port 1. I can verify your kernel-
config if you send me a copy. Are you running on a developer
board or have you built your own PCB?

-----Original Message-----
From: owner-dev-etrax@xxxxxxx.com]On">mailto:owner-dev-etrax@xxxxxxx.com]On
Behalf Of Anders Hasselqvist
Sent: Thursday, April 25, 2002 1:39 PM
To: dev-etrax
Subject: How does clk gated work?


We are using synchronus port 1 in master output mode.

Our problem is that the clock and frame sync is sent as soon as we turn
the serial port on. We only want them when actual data is sent.

We looked in the datasheets and found a clk gated option which
(as we understood) would do what we wanted.

But on our oscilloscope it seems like it's sending clk and frame sync
as soon as we enable clk running and tr enable.

Are we doing anything wrong?

Anders Hasselqvist/Björn Yttergren