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RE: Parallel portprinting problem
Happy to send patch at any time, however Axis are in the process
of reviewing my patch and explanations..
Ahhh I see they've just posted the diffs...
Ok all, well here is my explanation of the changes for those who are
Note: This is my own view of the world and I don't guarantee it is correct.
But it does work :-) (so far). Axis are looking into it.
First of all the internal etrax parallel port code is self consistent.
The linux code is also self consistent.
(Some of the linux lp documentation from memory does appear to be wrong
in its view of the polarity of Ack and Busy)
It's just that the two don't have the same logic conventions.
I have used the "/signal" convention to indicate an active low signal.
It is also important to point out to people that the signal line
interpretation is purely the printer's view of the world and that
"/SelectIn" for example does not imply anything about whether the parallel
port's output is inverted or not.
Note that the final column says "when register==1 Printer I/O is xx"
This means is that if the register/status bit is 1 then the printer line
(ie including any external hardware inverters etc) is set to xx where
xx is Active/Inactive logical state and high/low as a voltage (Vcc/Gnd).
PC/Linux parallel port View
Register/Status Nett_PC_Inv Signal_Line When Register==1 Printer I/O is
LP_PSELECP -ve /SelectIn Active (low)
LP_PINITP +ve /Init Inactive (high)
LP_AUTOLF -ve /AutoLF Active (low)
LP_STROBE -ve /Strobe Active (low)
LP_PERRORP +ve /Error Inactive (high)
LP_POUTPA +ve PaperOut Active (high)
LP_PSELECD +ve Select Active (high)
LP_PBUSY -ve Busy Inactive (low)
LP_PACK +ve /Ack Inactive (high)
Nett_PC_Inv is the nett inversion due to either the internal register
or the tranditional PC hardware (eg adding an inverter). These days of
I cannot tell which it used to be, and it no-longer really matters.
Etrax Parallel Port View
Note: The Config_Inv is how the Config register inversion is set for the
Driver. I have checked the logic and it is self consistent and therefore
The H/W_Inv is -ve if there is an IC inverter on the outputs (refers to
Developer 100LX board). Other harwdare developers can insert their own
values and create a valid matrix for them if you wish to publish my
(you are welcome provided you leave my name and email address in).
Chip_Pin is what happens at the output pin of the Etrax chip. It appears
that active-low OUTPUT pins are inverted internally so that "1" in the
maps to "0" for those pins (assuming Config_Inv is 0).
However no INPUT pins are inverted, regardless of active high/low
The nett effect of two "-ve" is that they obiously cancel one-another out
so three "-ve" equals one net inversion.
The lines marked *DIFF are different between Etrax and PC in terms of a
"1" in reg
gives a specific output at the printer. These pin could be inverted in
register if required to make like simpler for the PC person but the code
Register/Status Config_Inv Chip Pin H/W_Inv Signal_Line When Reg==1
Printer I/O is
PSELIN -ve -ve -ve /SelectIn Active (low)
INIT -ve -ve -ve /Init Active (low) *DIFF
AUTOLF/FD -ve -ve -ve /AutoLF Active (low)
STROBE -ve -ve -ve /Strobe Active (low)
PERROR (Fault) +ve +ve +ve /Error Inactive (high)
POUT +ve +ve +ve PaperOut Active (high)
SEL +ve +ve +ve Select Active (high)
BUSY +ve +ve +ve Busy Active (high) *DIFF
ACK +ve +ve +ve /Ack Inactive (high)
Meeting of the Worlds
PC-lp.c reg refers to the lp.c linux code and how it sets registers (taken
from PC View)
Etrax reg regers to extrax driver (taken from Etrax view)
Mapping is the mapping required to convert between the two worlds.
As can be seen there are two incompatibilities.
Register/Status PC-lp.c MAPPING Etrax
reg=1-> reg=1-> Signal_Line
PSELIN Act 1-1 Act /SelectIn
INIT Inact INVERT Act /Init
AUTOLF/FD Act 1-1 Act /AutoLF
STROBE Act 1-1 Act /Strobe
PERROR (Fault) Inact 1-1 Inact /Error
POUT Act 1-1 Act PaperOut
SEL Act 1-1 Act Select
BUSY Inact INVERT Act Busy
ACK Inact 1-1 InAct /Ack
With the above changes, doing a cat < /proc/sys/.../autoprobe
now returns info from my IEE1284 compliant device in reverse nibble
mode (I think) and my printers no-longer hang.
As a foot note I think that the unusual inversion of INIT and BUSY in the
is confusing and illogical.
All the other cases "make sense" because setting the register to 1
the relevant line for outputs and all the the inputs are straight through
from BUSY which inverts....