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I've modified the R_WAITSTATES register in order to add some wait states for a 
external peripheral located in csp0 address area.

Using "make xconfig"  I change the default value 95f8 to ff95f8.

		I expect to have : zw (turn off wait states) = 3
				   ew (early wait states) = 3
				   lw (late wait states) = 15
When I look at the signals on the Etrax bus for exemple the delay between
csp0 and rd, ew seems to be 0.

It seems that the change in this register has no effect on the bus timing ...

Does anyone have an idea ?

Best regards

Claude GIRERD 
Institut de Physique Nucleaire de Lyon
4, rue Enrico Fermi (Campus de la DOUA)
69622 Villeurbanne Cedex
tel: 04 72 44 83 96
fax: 04 72 43 14 52
email: girerd@xxxxxxx.fr