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Re: packet drops in the ETRAX100LX ethernet

Thanaks to Per Zander,

I have tested ETRAX100LX revision 2 and 3,
PHY as Broadcom BCM5221 in auto-MDIX mode,
and RJ45 with transformer as Speedtech P52-111-1AG9.

When using revision 2, all is OK.
And when revision 3 and 10BASE-T hub or PHY chip in 10BASE-T mode,
it's OK, there's no packet loses.

But when using revision 3 and 100BASE-TX mode,
there's many packet loses and network bootloading is impossible.

I have tested for 6 PCBs of revision 3,
the result is same,

I have fixed the H/W as Per Zander's guide,
but it's not operated in 100BASE-TX mode.

Best Reagrds,
Hyojun Kim.

----- Original Message ----- 
From: Per Zander <per.zander@xxxxxxx.com>
To: <dev-etrax@xxxxxxx.com>
Sent: Thursday, June 06, 2002 11:42 PM
Subject: RE: packet drops in the ETRAX100LX ethernet

> Hi, 
> The older model "AXT6212 17854 A0147" is mask revision 2 
> and the newer   "AXT6212 18816 A0214" is mask revision 3.
> The differences between the two versions of ETRAX 100LX (part numbers
> 17854 and 18816) are limited to small changes in the USB interface,
> and there are no design related differences that could effect the
> Ethernet operation.
> We have performed extensive Ethernet communication testing on both 
> mask revisions. The specific batch A0214 have been used in some of 
> these tests. No problems have been observed. 
> There may be some batch dependent variations in parameters like power
> consumption, signal threshold levels and output buffer speed, due to
> normal process variation. This kind of variation is taken into account 
> in the specification of ETRAX 100LX, and should not cause any problems 
> in a properly designed circuit.
> The problems you describe indicate that there is something marginal in 
> the design of the circuit board, that makes it sensitive to batch
> variation. Typical problem areas are:
> - System clock (20 MHz).
>   Jitter, noise and/or improper termination on the clock signal may
>   affect the operation of the internal PLL in ETRAX 100LX. Too low 
>   amplitude of the system clock (e.g. because of EMI suppression)
>   may also result in batch dependent problems. 
> - Transceiver clock.
>   Crosstalk and/or improper termination of the 25 MHz clock to the 
>   transceiver may cause packet loss.
> - PLL loop filter.
>   Improper layout of the PLL loop filter may introduce noise that
>   affects the stability of the internal PLL.
> - Insufficient decoupling or improper grounding.
>   This may cause batch dependent problems, since variations in power 
>   consumption and output buffer speed vill affect the amount of
>   ground bounce and power ripple on the board. 
> Best regards
> Per Zander