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Re: Some thoughts on ethernet.c




> According to the IEEE Std 802.3, the PHY should output its data in
> response to the positive edge of mdc, with a maximum delay of 300 ns.

Actually, yes. Our LSI Logic datasheet shows a clock so fast that it's
leading the data output by nearly 180 degrees ;)

> I could not say. Is there something in between the ETRAX 100LX and the PHY
> that adds delay ?

Yes, the resistors I mentioned, slightly too large.


Jarkko


--
Jarkko Tuomi jtuomi@xxxxxxx.fi/~jtuomi/">http://www.hut.fi/~jtuomi/