[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

caching mechanism

I've got a question about Etrax internal databus caching.

If i write "X" to address 80000000 (uncached),
then read "X" from 0 (same but cached),
then write "Y" to address 80000000 (uncached),
what can I read from address 0 now? X or Y?

Is the caching mechanism aware of that whatever was read from 0 should 
be reread since I've forced a write to same place in hw?