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RE: caching mechanism
The cache does not guarantee consistency in this case. If X is
still in the cache you would get X otherwise Y. You can see some
comments about this in arch/cris/drivers/axisflashmap.c. I would
recommend that you run either all accesses cached or all accesses
uncached. What kind of device are you interfaceing with?
Behalf Of Ronny L Nilsson
Sent: Wednesday, August 14, 2002 9:34 AM
Subject: caching mechanism
I've got a question about Etrax internal databus caching.
If i write "X" to address 80000000 (uncached),
then read "X" from 0 (same but cached),
then write "Y" to address 80000000 (uncached),
what can I read from address 0 now? X or Y?
Is the caching mechanism aware of that whatever was read from 0 should
be reread since I've forced a write to same place in hw?