[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
RE: ETRAX 100LX Bus Status
If BS3=0 at reset the pins have the output described below. These outputs
used together with the logic analyzer mode.
Codes 0-9 are used for DMA status. The DMA channel number (0-9) is
output at the start of each DMA operation, related to the DMA clock
phase C. For a DMA restart or stop operation, the code '9' is then
output related to DMA clock D. For input channels with eop set,
the number of remaining bytes in the FIFO is output for one cycle
(related to DMA clock D) when it goes down to 8 or lower.
Codes 10-15 are used for the CPU interrupt status:
10 IRQ with external vector number, no NMI.
11 IRQ with external vector number, and NMI.
12 No IRQ, no NMI.
13 NMI, but no IRQ.
14 IRQ with internal vector number, no NMI.
15 IRQ with internal vector number, and NMI.
From: firstname.lastname@example.org]On">mailto:email@example.com]On Behalf Of
Sent: Friday, August 30, 2002 12:13 AM
Subject: ETRAX 100LX Bus Status
Can someone tell me how to interpret the bus status bits (bs0...bs3) when
the reset sequence has completed?