[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: ETRAX 100LX Bus Status




On Thu, 29 Aug 2002, Chris Nickles wrote:

> Hello,
> 
> Can someone tell me how to interpret the bus status bits (bs0...bs3) when 
> the reset sequence has completed?
> 
> Thanks,
>     Chris Nickles
> 

After the reset sequence, BS0-BS3 are used for DMA and CPU status.
BS0-BS3 will only be output if BS3 is low when RESET_ goes inactive.

Codes 0-9 are used for DMA status. The DMA channel number (0-9) is
output at the start of each DMA operation. For a DMA restart or stop 
operation, the code '9' is output. For input channels with eop set,
the number of remaining bytes in the FIFO is output for one cycle
when it goes down to 8 or lower.

It is not easy to figure out if it is a DMA channel number or the
restart/stop/number of bytes case.  
 
Codes 10-15 are used for the CPU interrupt status:

 10  IRQ with external vector number, no NMI.
 11  IRQ with external vector number, and NMI.
 12  No IRQ, no NMI.
 13  NMI, but no IRQ.
 14  IRQ with internal vector number, no NMI.
 15  IRQ with internal vector number, and NMI.

Per Zander