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RE: Altera Acex EP1K50 and syncser0
With inverted clock the sequence should be like this:
Clock high (default)
Set data value
I am not sure about the exact clock timing in relation to the data output.
From: firstname.lastname@example.org]On">mailto:email@example.com]On Behalf Of Terje Pedersen
Sent: Monday, November 18, 2002 1:24 PM
Subject: Altera Acex EP1K50 and syncser0
1. Is there anybody out there who has tried to use syncser0 to upload programming data to an Altera PLD chip using the passive serial configuration scheme? (data0,nstatus,conf_done,dclk,nconfig) (The missing action is CONF_DONE going high.)
2. The PLD chip reads the data at the positive edge of dclk demanding that the data is out before the clock. Is it possible to delay the clock in software other than inverse the clock with CLOCK_INVERT? If using the inverted clock what is happening at start? Is the clock low to the middle of the first data bit?
Jakob Hatteland Computer