[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: Altera Acex EP1K50 and syncser0



I managed to get a working uploader program yesterday, so its possible to
use the inverted clock (CLOCK_INVERT) to get the desired delay between data
and clk when programming an Altera PLD chip. But the reason it wouldn't work
earlier was because I sendt to much data at once to the PLD a total of
98023bytes (.rbf file). When I tested with somewhere more than 60000 bytes
at once it wouldn't work (the outputbuffer in syncser driver was enlarged).
Either this is a limit by the PLD chip which is not documented or it could
be the syncser driver not working with large buffers.

Terje Pedersen
Jakob Hatteland Computer


----- Original Message -----
From: "Mikael Starvik" <mikael.starvik@xxxxxxx.com>
To: "'Terje Pedersen'" <terje.pedersen@xxxxxxx.com>; "dev-etrax"
<dev-etrax@xxxxxxx.com>
Sent: Monday, November 18, 2002 1:37 PM
Subject: RE: Altera Acex EP1K50 and syncser0


> With inverted clock the sequence should be like this:
>
> Clock high (default)
> Clock low
> Set data value
> Clock high
>
> I am not sure about the exact clock timing in relation to the data
> output.
>
> /Mikael