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From the board design point of view, PLLVSS is a normal VSS (i.e. ground).
pin. It is one of the VSS pins listed in the data sheet (V10). There is no
need to treat this pin in any other way than the other VSS pins. I don't 
know why it is treated separately in the dev. kit schematics.

There are two other minor errors in the dev. board schematics. The PLL
loop filter connections are labeled PLLP2 and PLLLAGN. The correct names
are PLLLP2 and PLLAGN.

Per Zander                      email: per.zander@xxxxxxx.com
Axis Communications AB          Tel:   +46 46 272 18 25 
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On Wed, 15 Jan 2003, Alex Raimondi wrote:

> Hi
> In the shematics of the devkit i can finde a pin named PLLVSS but I can't
> read anything
> about it in datasheet.
> Which number has this pin?
> Thanks Alex