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Re: External DMA interrupts
See my questions and answers below.
On Thu, 6 Mar 2003, Arne Bockholdt wrote:
> we trying to use the external DMA to communicate with a FPGA on our custom
> design. We're using external DMA 0 only in output direction and in bust
> mode. The associated internal DMA channel is 4. I get some weird results
> when I playing with the d_wait flag in the descriptor, instead of one
> interrupt I get three when using only one descriptor.
Which interrupts do you get ? The internal DMA channel 4 can generate
the dma4_eop and the dma4_descr interrupt. The external DMA channel
can generate the ext_dma0 interrupt.
The dma4_eop and dma4_descr interrupts are generated when the
corresponding descriptor has been completely processed (given that the
eop and intr bits are set in the descriptor). If the wait bit is
set in the descriptor, the interrupts are delayed until the DMA FIFO
has been emptied. Without the wait bit, the DMA generates the interrupts
and continues with the next descriptor (if any) as soon as all data
is read from memory into the FIFO.
The ext_dma0 interrupt is generated when the external DMA channel is
stopped. It can be stopped for three reasons:
1. SW stopped it.
2. End of packet was set from the internal DMA channel.
3. The transfer counter in the external DMA channel expired.
> * How can I be certain that a DMA transfer has been completed ? The
> descriptor status isn't updated. Is there any flag that indicates the end
> of transfer ?
The R_DMA_CH4_FIRST register holds the address to the first descriptor
of the current packet (packet == chain of descriptors, ending with
a descriptor with the eop bit set). If the DMA has completely processed
a descriptor with the eop bit set, it will update R_DMA_CH4_FIRST to
the next descriptor. If it is also end of list, there is no next
descriptor and R_DMA_CH4_FIRST will be set to 0.
> * Is there any way to find out why the DMA has been stopped ? (IO has
> dropped DREQ or end of transfer) ?
If you use the eop bit in the descriptor, that will propagate
to the external DMA channel and stop it, so you could check the
R_EXT_DMA_0_STAT run bit.
> * There seems to be no way to see why I received a ext_DMA interrupt. The
> internal DMA has a register to get the reason for the interrupt. Where is
> the data for the external DMA ?
There is onlu one reason: The channel is stopped. Se above for
reasons for stopping. DREQ inactive does not stop the channel,
it just "pauses" it.
> * Without the d_wait flag I receive one interrupt, with the flag three of
> them. Why ?
Hard to say without reviewing your exact application in detail.
> * Has the d_intr flag any meaning for output transfers ?
It could have, but it depends on what you want to do.
It indicates that the descriptor is completely processed, and
this may or may not be useful.
> * Is there any additional documentation about the external DMA ? I got the
> ET100LX_07_DMA_011019.pdf but the chapter about the external DMA is very
Don't think there is anything that is relevant to send you, but I'll
> Thannk you in advance,
> Arne Bockholdt
> Dipl. Inform. Arne Bockholdt
> REA Elektronik GmbH
> Teichwiesenstr. 1
> 64367 Mühltal-Waschenbach
> Tel. +49 (0) 6154 / 638-115, Fax -195