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Re: Shut down the memory bus (for a while)




The delay from the write to the actual setting of the GP pin is
in the range of 20-40 ns (from the end of the bus cycle).
This is short but you could not definitely exclude the possibility
that another bus cycle will be started during this time.

Per Zander                      email: per.zander@xxxxxxx.com
Axis Communications AB          Tel:   +46 46 272 18 25 
Emdalavagen 14                 Fax:   +46 46 13 61 30
SE-223 69 LUND, SWEDEN          Visit our web site: http://www.axis.com/

On Tue, 10 Jun 2003, Bernhard Mäder wrote:

> Hi Per
> 
> Thanks for the fast reply.
> 
> Uh, seems a lot of work to do....
> 
> One thing I wonder: after a write to the R_PORT_G_DATA register, how fast
> will the GP pin drive the requested level? If it's directly connected to
> that register, I wonder if it wouldn't suffice to ensure that before writing
> R_PORT_G_DATA (pulling the reset_n high), bit 5 of the data bus has to be
> set. I'd just write to the register twice, first setting bit 5 and then
> pulling the reset high. Since that config pin is sampled at the reset's
> rising edge, the DSP doesn't bother for values of that pin during or after
> reset.
> 
> Or is that too simple?
> 
> Best regards and thanks a lot!
> Bernhard
> 
> ----- Original Message ----- 
> From: "Per Zander" <per.zander@xxxxxxx.com>
> To: "Bernhard Mäder" <bmaeder@xxxxxxx.ch>
> Cc: "Per Zander" <per.zander@xxxxxxx.com>
> Sent: Friday, June 06, 2003 5:30 PM
> Subject: Re: Shut down the memory bus (for a while)
> 
> 
> > Hi again,
> >
> > I guess that you, in addition to stopping the DMA and making sure
> > that you run from internal cache, also have to make sure that
> >
> > a) you write to the whole 32 bits of the R_PORT_G_DATA when you
> > activate and deactivate the DSP reset, and that you have bit 5 set
> > to 1 in these writes
> >
> > and
> >
> > b) you do not read or write any other internal mode registers
> > during the reset process
> >
> > and
> >
> > c) you do not have any interrupts running, since interrupt acknowledge
> > cycles will also cause bus activity.
> >
> > Unfortunately this is not really what I would call "simple" but I
> > think it would work.
> >
> > Best regards
> >
> > Per Zander                      email: per.zander@xxxxxxx.com
> > Axis Communications AB          Tel:   +46 46 272 18 25
> > Emdalavagen 14                 Fax:   +46 46 13 61 30
> > SE-223 69 LUND, SWEDEN          Visit our web site: http://www.axis.com/
> >
> > On Fri, 6 Jun 2003, Bernhard Mäder wrote:
> >
> > > Hi Per
> > >
> > > Thanks for the fast reply! The DSP's Reset_N is connected to the G24 pin
> > > (E19). The pullup resistor is located at data pin D5 (J3).
> > >
> > > Thanks
> > >  Bernhard
> > >
> > > ----- Original Message ----- 
> > > From: "Per Zander" <per.zander@xxxxxxx.com>
> > > To: "Bernhard Mäder" <bmaeder@xxxxxxx.ch>
> > > Cc: "dev-etrax" <dev-etrax@xxxxxxx.com>
> > > Sent: Friday, June 06, 2003 4:38 PM
> > > Subject: Re: Shut down the memory bus (for a while)
> > >
> > >
> > > > Hi Bernhard,
> > > >
> > > > I'm afraid it might not help to only run through internal cache and
> > > > disable the DMA. The writes to the internal IO in Etrax are visible
> > > > on the data bus anyway and the problem may be caused by these
> > > > bus cycles. If you tell me exactly which data pin and which GP pin
> that
> > > > are used I might be able to say whether there is a simple solution or
> not.
> > > >
> > > > Best regards
> > > >
> > > > Per Zander                      email: per.zander@xxxxxxx.com
> > > > Axis Communications AB          Tel:   +46 46 272 18 25
> > > > Emdalavagen 14                 Fax:   +46 46 13 61 30
> > > > SE-223 69 LUND, SWEDEN          Visit our web site:
> http://www.axis.com/
> > > >
> > > > On Fri, 6 Jun 2003, Bernhard Mäder wrote:
> > > >
> > > > > Hi all
> > > > >
> > > > > We've built a DSP plattform using an Etrax for interfacing. The
> etrax is
> > > > > also booting up the Ti DSP via its host port interface, which is
> > > directly
> > > > > connected to the etrax' memory bus. This interface is selectable to
> be
> > > > > either 16 or 32 bits wide, which is done with a pull-up or -down
> > > resistor on
> > > > > one of the data pins.
> > > > >
> > > > > This all works fine when booting the DSP and the Etrax at the same
> time,
> > > but
> > > > > resetting the DSP during operation is impossible because that very
> data
> > > pin
> > > > > is apparently driven to the wrong level each time we try. It appears
> > > that,
> > > > > when going through the code to reset the DSP (which is done with a
> GP
> > > pin
> > > > > connected to the DSPs reset), the same access pattern is sent
> through
> > > the
> > > > > bus.
> > > > >
> > > > > Does anyone know how I best bypass this problem? I thought of
> somehow
> > > using
> > > > > the internal cache and disabling DMA transfers to be sure that the
> > > memory
> > > > > bus is clean for some time....
> > > > >
> > > > > Thanks a lot
> > > > >  Bernhard
> > > > >
> > > >
> > > >
> > >
> >
> >
>