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RE: Etrax100LX SDRAM problem


Sorry that you didn't receive any reply from us. The CAS latency affects two
values in the SDRAM configuration sequence:

1. CAS latency value in R_SDRAM_TIMING
2. Value used in the mrs cycle. In your case you do  --setreg b0000008 8000c202
   close to the end of the sequence. In this command mrs_data should be set in
   bits 16-23 with the following value:

   CL = 2, buswidth = 32 => 0x40
   CL = 3, buswidth = 32 => 0x60
   CL = 2, buswidth = 16 => 0x20
   CL = 2, buswidth = 16 => 0x30

(e.g. 0x8040c202)

Normally boot_linux does this for you.

PS. CL=2 results in higher performance. DS


-----Original Message-----
From: owner-dev-etrax@xxxxxxx.com">mailto:owner-dev-etrax@xxxxxxx.com] On Behalf Of Pieter Grimmerink
Sent: Tuesday, June 10, 2003 12:07 PM
To: dev-etrax
Subject: RE: Etrax100LX SDRAM problem

On Wednesday 04 June 2003 00:48, Pieter Grimmerink wrote:
> --setreg b0000008 80008002\
>  --setreg c0000000 12345678\
>  --getreg c0000000
> The result that getreg returns is 12341234.
> The upper two bytes seem to be read (or written...) twice.
> Is this a problem with my configuration?

Indeed, it turned out to be a problem with my config. For some reason, setting the CAS latency to 3 caused this. According to my SDRAM specifications, both 2 and 3 CAS latency cycles are supported. Looks like the etrax does not configure the SDRAM properly, or something else is wrong. Anyway, it works fine now with

--setreg b0000008 80008001

so I don't care too much to find the exact reason ;-)