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Re: gpio question on Axis82



OK, it turns out that the pins are working correctly on the ETRAX, but the NAND
gate - D25 on the devboard 82 doesn't seem to be behaving properly.  according
to the schematic, the output pins shouldn't have any resistors connected, but
they certainly don't change when the inputs change.  Could this be a problem
with the chip or is there something in the schematic that I'm missing?

Kevin Wooley wrote:
> 
> I'd like to use the gpio pins g1-g4, which are available through a NAND gate on
> header pinx X23.
> 
> using this basic test program below, the pins don't seem to change.  The pins
> are multiplexed to a bunch of devices, but I'm pretty sure I've disabled
> everything in the kernel config except for Shared-RAM, sicne I'm not sure where
> to configure that.  According to the schematic, the pins aren't connected to
> anything else, so I think they should be available for use.  How do I ensure
> that Shared-RAM is disabled?  is this the same thing as SDRAM (I don't think
> so).  Is there something else I need to do?
> 
> thanks,
> 
>         Kevin
>