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RE: Design hint wanted...
I would suggest using the external DMA. When the device has data to
send it can signal ETRAX on dreq. When ETRAX is ready it will tell
the device to send the data by setting dack (and a chip select
if the external DMA is configured correctly). You can configure
the external DMA to transfer 8, 16 or 32 bits in each transfer.
You can read about the external DMA in
Another option would be 16-bit ECP on the parallel ports but that
would require more work in hardware.
Have you ever thought of doing the minimum value stuff in hardware
instead? If you need an FPGA for other reasons you could put it