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Re: Etrax 100Lx MCM8+2 + 2 external flashes
OK, thanks for your prompt reply.
That means, if the two chips are both accessible and contiguous in the
mapping thanks to the external logic, the MTD probe stuff will discover both
of them automatically, right ? Or is it required to patch axisflashmap.c in
the kernel, in order to test cse1_a at 0x04000000 first, then cse1_b at
----- Original Message -----
From: "Mikael Starvik" <email@example.com>
To: "'Johann Dantant'" <firstname.lastname@example.org>; "dev-etrax"
Sent: Thursday, March 04, 2004 7:26 AM
Subject: RE: Etrax 100Lx MCM8+2 + 2 external flashes
> ETRAX 100LX has two flash chip selects:
> cse0: 0x00000000
> cse1: 0x04000000
> You can use two flashes on cse1 by adding external logic that
> activates the first flash at 0x04000000 and the second at
> 0x04200000. So CE for the first flash is !(!CSE1 & !A21) and
> !(!CSE & A21) for the second. DeMorgan's theorem is useful
> to transform them into CSE1 |A21 and CSE1 |!A21.
> There is one ETRAX customer who uses 4*8 MB on CSE1 :-)