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Connecting Peripheral to system bus



Hi,
I want to make a tiny mobile platform based on a ETRAX 100LX MCM. The
platform will look like a single MCM + several system slots. These slots
could be used to insert memory modules and peripheriental devices. This
would favor flexibility and yield reducing risks. Do you think it is a good
idea? Please, criticise this idea. I'm far from being an expert in
high-frequency designs.

The design I'm working on is a multi-channel voice recording system. I was
thinking about usig ETRAX for sound stream -> VoIP converter. Data is
acquired from several ADCs and stored in dual-port memory. This will be done
by FPGA. When the buffer accumulates several kilo samples (about a second),
ETRAX reads the buffer from second memory port at high speed using system
bus (and DMA?). I'm sure this architecture allows for very efficient use of
single-chip computer. The memory buffer can be located and served by FPGA
single chip. Thinking about FPGA - ETRAX interface I'm having some
questions.

1. There are series resistors used at DATA and CLK lines on the SDRAM
implementation examples. What is their purpose? Where is their location if
more than one memory/device is connected to the bus?
2. ETRAX uses bursts accessing system bus. Is it typical for peripheriental
acces to put all those "Early wait states", "Late wait states" and "Turn-off
wait states" into zero, so that read operation is performed at each rising
clk edge?
3. What is the reason for *chip selects*, e.g. cse, csr csp? IMO, they are
redundant because allow for conflicts. For example, device from csp3 area
responds to addresses corresponding to csp4 widow.
4. Section "5.6 - Memory Timing" of Bus_Interface.pdf shows that data are
sampled at rising /RD signal. As far as I'm aware of synchronous digital
designs, this is rising edge of CLK that should change state of automata
registers. Meantime, /RD should be stable setup time before CLK edge. Why
CLK is not shown and wait cycles depend on RD rather than CLK?
5. Thre is one read controlling signal (RD_). Why does the chip has 4 write
controlling signals (WR0_ - WR3_)?
6. What is shared RAM? Why DMA cannot be used for direct shared memory
access.
7. I cannot find specification of I2C bus. What is its purpose (general or
SDRAM initialization) and speed?


As you see, I have many stupid questions. Axis site recommends lost of
literature about Linux SW writing. May be there is *a must* reading about
the HW concepts of attaching peripheral that you can recommend for a
beginner like me?


Thank you very much.