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Re: Connecting Peripheral to system bus
I hope someone corrects me if I'm wrong, but I'll try to answer
your questions below.
----- Original Message -----
From: "valentin tihomirov" <email@example.com>
Sent: den 13 mars 2004 17:07
Subject: Connecting Peripheral to system bus
> I want to make a tiny mobile platform based on a ETRAX 100LX MCM. The
> platform will look like a single MCM + several system slots. These slots
> could be used to insert memory modules and peripheriental devices. This
> would favor flexibility and yield reducing risks. Do you think it is a
> idea? Please, criticise this idea. I'm far from being an expert in
> high-frequency designs.
I guess the risk of high emission is fairly large, and depending on the
use it might not be cost effective to have external modules.
I'm not an expert on high frequency design either, but I've done some FPGA
> The design I'm working on is a multi-channel voice recording system. I was
> thinking about usig ETRAX for sound stream -> VoIP converter. Data is
> acquired from several ADCs and stored in dual-port memory. This will be
> by FPGA. When the buffer accumulates several kilo samples (about a
> ETRAX reads the buffer from second memory port at high speed using system
> bus (and DMA?). I'm sure this architecture allows for very efficient use
> single-chip computer. The memory buffer can be located and served by FPGA
> single chip. Thinking about FPGA - ETRAX interface I'm having some
Does the dual port memory has an SDRAM or an SRAM type interface?
If it's an SRAM type of interface, I think connecting it to chip select csr0
have the FPGA memory mapped on csp0 so you can have different wait state
> 1. There are series resistors used at DATA and CLK lines on the SDRAM
> implementation examples. What is their purpose?
I think they are there to reduce emission (EMI).
>Where is their location if
> more than one memory/device is connected to the bus?
I believe they should be located as close as possible to the source of the
ie. the MCM chip.
> 2. ETRAX uses bursts accessing system bus. Is it typical for
> acces to put all those "Early wait states", "Late wait states" and
> wait states" into zero, so that read operation is performed at each rising
> clk edge?
I would say that a typical peripheral wouldn't use the SDRAM interface so
SDRAM clk is not really applicable.
A read operation could either be clocked by the _rd signal for an
or the _rd signal would have to be synchronised with the FPGA clk (using two
If you can use the _rd as a clock signal in the FPGA for some of the logic
you should be careful when communication between clock domains.
In the second case, the number of waitstates depends on the FPGA clock
and how the synchronisation is done.
> 3. What is the reason for *chip selects*, e.g. cse, csr csp? IMO, they are
> redundant because allow for conflicts. For example, device from csp3 area
> responds to addresses corresponding to csp4 widow.
Chip selects make it easier to have different type of peripherals without
glue logic doing address decoding.
An external device connected to the bus should _always_ use one of the
chip select as part of its address decoding.
> 4. Section "5.6 - Memory Timing" of Bus_Interface.pdf shows that data are
> sampled at rising /RD signal. As far as I'm aware of synchronous digital
> designs, this is rising edge of CLK that should change state of automata
> registers. Meantime, /RD should be stable setup time before CLK edge. Why
> CLK is not shown and wait cycles depend on RD rather than CLK?
5.6 describes access to asynchronous devices, typically SRAM, flash memory
Se my answers under point 1 as well.
Se chapter 20 for more details on bus timing.
> 5. Thre is one read controlling signal (RD_). Why does the chip has 4
> controlling signals (WR0_ - WR3_)?
To control what bytes of the bus that are written - it allows you to write a
in a memory connected with a 32 bit wide databus.
For read, ETRAX does the "right thing" and discards read data not needed,
although you shouldn't have a peripheral that you must access bytewise for
> 6. What is shared RAM? Why DMA cannot be used for direct shared memory
Shared RAM is typically used to communicate with some printers.
Sorry, don't know any details.
> 7. I cannot find specification of I2C bus. What is its purpose (general or
> SDRAM initialization) and speed?
There really is no spec - it's only a couple of pins suggested to be used
(and som minor register support) but the bittoggling is all done in
It's use is general - typically for RTC and eeprom.
> As you see, I have many stupid questions. Axis site recommends lost of
> literature about Linux SW writing. May be there is *a must* reading about
> the HW concepts of attaching peripheral that you can recommend for a
> beginner like me?
is pretty basic, but it's a start.
> Thank you very much.
Hope that helped