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Re: Connecting Peripheral to system bus
I think Johan covered most of it, but I will try to fill in
a few things that was not so clear in his answer. See below.
On Sat, 13 Mar 2004, valentin tihomirov wrote:
> I want to make a tiny mobile platform based on a ETRAX 100LX MCM. The
> platform will look like a single MCM + several system slots. These slots
> could be used to insert memory modules and peripheriental devices. This
> would favor flexibility and yield reducing risks. Do you think it is a good
> idea? Please, criticise this idea. I'm far from being an expert in
> high-frequency designs.
> The design I'm working on is a multi-channel voice recording system. I was
> thinking about usig ETRAX for sound stream -> VoIP converter. Data is
> acquired from several ADCs and stored in dual-port memory. This will be done
> by FPGA. When the buffer accumulates several kilo samples (about a second),
> ETRAX reads the buffer from second memory port at high speed using system
> bus (and DMA?). I'm sure this architecture allows for very efficient use of
> single-chip computer. The memory buffer can be located and served by FPGA
> single chip. Thinking about FPGA - ETRAX interface I'm having some
> 1. There are series resistors used at DATA and CLK lines on the SDRAM
> implementation examples. What is their purpose? Where is their location if
> more than one memory/device is connected to the bus?
One reason is to reduce EMI, as Johan mentions. Another reason is
to reduce ringing on the signals, thus improving the noise margin.
> 2. ETRAX uses bursts accessing system bus. Is it typical for peripheriental
> acces to put all those "Early wait states", "Late wait states" and "Turn-off
> wait states" into zero, so that read operation is performed at each rising
> clk edge?
I would say that peripheral devices typically require at least one
"early wait state" and often one or more of the other types of
waitstates too. But it depends very much on the peripheral device.
> 3. What is the reason for *chip selects*, e.g. cse, csr csp? IMO, they are
> redundant because allow for conflicts. For example, device from csp3 area
> responds to addresses corresponding to csp4 widow.
There is no conflict. The internal address is 31 bits (the most
significant bit is the cached/non-cached bit). The external address bus
contains address bits 25:1 (address bit 0 is not needed externally since
the data bus is always at least 16 bits wide). The chip selects are decoded
from the internal address bits 30:26 and there is of course no overlap
> 4. Section "5.6 - Memory Timing" of Bus_Interface.pdf shows that data are
> sampled at rising /RD signal.
It actually does not show _how_ data is sampled, only (in a very
simplified way) _when_ it is sampled. As Johan mentioned, go to
chapter 20 for detailed timing.
> Why CLK is not shown
CLK is an internal signal not immediately available to the user.
Therefore, it is not shown.
> and wait cycles depend on RD rather than CLK?
It's the other way around. The behaviour of the RD signal depends
on whether the "early wait states" are 0 or >0.
> 5. Thre is one read controlling signal (RD_). Why does the chip has 4 write
> controlling signals (WR0_ - WR3_)?
> 6. What is shared RAM?
The shared RAM interface is an interface used in some printer
applications, as Johan mentioned. The principle is described
in chapter 15. It allows the printer to share a part of ETRAX 100LX's
system memory (it must be SRAM in that case). I don't think this
interface is suitable for your application.
> Why DMA cannot be used for direct shared memory access.
Johan didn't answer this, and I do not completely understand
the question. The DMA can make peripheral->memory, memory->peripheral
and memory->memory transfers. There is no general problem with
using DMA to/from external memories or external peripherals.
It might very well work in your application, but it is hard to
say without knowing the details of what you want to do.
Look at the DMA chapter (chapter 7). DMA to external peripherals
is described in the end of the chapter.
> 7. I cannot find specification of I2C bus. What is its purpose (general or
> SDRAM initialization) and speed?
> As you see, I have many stupid questions. Axis site recommends lost of
> literature about Linux SW writing. May be there is *a must* reading about
> the HW concepts of attaching peripheral that you can recommend for a
> beginner like me?
> Thank you very much.