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Re: Finalized TODO list for NAND and JFFS...
> By the way, can't we shorten mount time for Intel chips by rewriting
> read routines in such a way that they don't send Read Status Register
> command when chip->status is FL_READY?
Yes - well spotted.
> So the question, as I can see it, is can we be sure that Status
> Register has 7th bit set when chip->status == FL_READY?
Yes. If that's ever _not_ the case, then consider it a bug in whatever code
is setting the state to FL_READY.
Please supply either a SSH public key, so I can give you write access to
CVS, or a patch that I can apply. The former is probably better.