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RE: $subject

On Sat, 3 Mar 2001, Vipin Malik wrote:

> From the mode of failure (erase never completing because of 
> async pwr down), I would expect to encounter this problem only
> during power down testing. How did you encounter this? Are you
> doing power down testing too?

No, just 'reboot -f' on the iPAQ. I did power-down testing on Intel 
Strataflash at one point, but didn't encounter this behaviour.

> In my "patch" to fix for non aligned offsets I only accept free spaces
> that are at least 1 erase sector long. But I guess that any trailing
> space into the next sector may have this problem.
> David, is it correct if I assume, that we must correctly identify the
> head and tail of the log, during mount, which corresponds to the
> head and tail of the fs log that the system had *last time*, i.e.
> before power failed?

You don't have to. You want to use the largest free space, and that's 
almost always going to be between the head and tail that the system had 
last time - I can't imagine how it would be different. 

> ..but from this comment the above (what I wrote) does not seem to be
> true. It seems that the system will behave correctly regardless
> of where the head and tail end up on every new mount, as long as
> there is enough free space between the two?


> Which would mean erasing the entire flash on a empty or mostly empty
> file system. Would it be faster to scan all free spaces, 3 or 4 times,
> and accept it as free and ok if it scanned free every time and
> erase it if even 1 bit is found to be not a "1".

That's a more realistic possibility, yes.

> > To avoid this, it's advisable to call the MTD power management
> > suspend() call before powering down the device in normal operation,
> > and unless it's absolutely necessary, only continue with the power
> > down if it/when returns 'OK'.
> Well, either it works fine after all (read > 5000) power down tests
> or not. If it works fine even in power down then why
> bother with the "special handling"?

Good point. 

> My previous power down test experience has shown that any weakness
> in the system is usually found within a few hundred cycles.
> If the system passes about 1500 cycles, it will run to 5000+ cycles
> without any problem. And if you do the math- for "regular" systems
> which are not that flash write happy (as my test is) 5000+ cycles
> of reliable operation would map to a miniscule failure rate in the field
> even if there is still a problem that was not detected in the tests.
> At least I would be happy with it. Considering so many embedded
> systems are shipped with nary a power down test, we would be way
> ahead in the game :)
> David, any day of the week you'r not working ;)

Monday morning usually :)


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