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RE: Axis' JFFS
> Briefly: I encountered a problem during power fail testing
> where a bit(s)
> would flip between "1" & "0" if you read it (them) multiple times.
> I've hypothesized that this occurs when power fails during an
> erase. Just
> enough charge remains trapped in the floating gate to cause the sense
> (read) amplifier for that bit to flip between a "1" & "0".
> This problem is
> fixed by re-erasing the entire sector which ensures that this
> amount of charge is filled up completely (or drained whichever is the
> erased state).
Silly question: could this have anything to do with the toggle bit (D6 on AMD
compatibles)? Maybe it's stuck in "toggle mode" after power up (wild guess)?
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