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Re: JFFS is not broken (Was: JFFS broken?)
> Yes, but the flash chips are slow so it doesn't help. The CPU has to
> wait for every word to be read into the cache.
Just to check we're talking about the same thing here - are you really
doing synchronous burst reads, or just filling a cache line with normal
async reads from the flash?
I don't expect much performance gain unless you do the former.
http://developer.intel.com/design/flcomp/datashts/290737.htm has details on
how some of the Intel StrataFlash chips do it...
"To perform synchronous burst-mode read, an address is driven onto A[max:1],
and CE# and OE# are asserted. WE# and RST# must be de-asserted. ADV# is
asserted, then de-asserted to latch the address. <...>
"<...> After the initial access delay, the first word is output from the
data buffer on the next valid CLK edge. Subsequent buffer data is[sic]
output on valid CLK edges. Synchronous burst-mode reads can only step
through the data buffer once, and can only do so in a sequential manner;
starting from the address latched at the beginning of the burst cycle."
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